The design of low noise oscillators

Contents 1 Introduction 2 Frequency Instability Fundamentals 2.1 2.2 Introduction to Frequency Instability 2.1.1 2.1.2 Frequency Domain Time Domain Frequency Instability Characterization 2.2.1 2.2.2 Phase Noise Timing Jitter 3 Review of Existing Models 3.1 3.2 Tuned-Tank Oscillators Ring Oscillators 1 2 5 5 6 8 9 10 13 vii 1.1 17 17 24 Organization THE DESIGN OF LOW NOISE OSCILLATORS 4 Time-Variant Phase Noise Model 4.1 Impulse Response Model for Excess Phase 4.2 4.3 4.4 4.5 4.6 4.7 4.8 Response to Sinusoidal Input 4.2.1 4.2.2 4.2.3 Perturbation Current-to-Phase Transformation Phase-to-Voltage Transformation Simulation and Experimental Verification Phase Noise and Jitter due to Random Noise 4.3.1 4.3.2 Phase Noise Phase Jitter Upconversion of Low Frequency Noise 4.4.1 4.4.2 Calculation of the Noise Corner Simulation and Experimental Verification Other Time-Variant Effects 4.5.1 4.5.2 Cyclostationary Noise Sources Voltage Dependent Capacitors Amplitude Response Relationship to Previous Models Summary 5 Jitter and Phase Noise in Ring Oscillators 5.1 The Impulse Sensitivity Function for Ring Oscillators 5.1.1 5.1.2 Equal Rise and Fall Times Unequal Rising and Falling Times 5.2 5.3 5.4 Expressions for Jitter and Phase Noise in Ring Oscillators 5.2.1 5.2.2 5.2.3 Single-Ended CMOS Ring Oscillators Differential CMOS Ring Oscillators Bipolar Differential Ring Oscillator Correlated Noise Sources Design Implications in Ring Oscillators 5.4.1 5.4.2 Differential vs. Single-Ended Optimum Number of Stages 5.4.3 5.4.4 Lowering the Effect of Correlated Noise Sources The Effect of Tail Current Noise Source 5.5 Experimental Results 5.6 Summary viii 31 31 41 41 44 45 48 49 54 55 55 61 65 65 69 71 75 77 79 79 80 84 86 87 90 92 93 96 96 98 99 99 100 110 CONTENTS 6 Phase Noise in Differential LC Oscillators 6.1 6.2 6.3 6.4 6.5 Tank Amplitude Noise Sources 6.2.1 6.2.2 Stationary Noise Sources Cyclostationary Behavior in the Presence of a Tail Capacitor Tail Current Noise Source Experimental Results and Design Implications Summary 111 111 114 116 117 119 121 128 7 Extension of the Model to Multiple Noise Sources 129 7.1 7.2 7.3 Phase Response Phase Noise due to Multiple Stochastic Noise Processes Summary 8 Conclusion A Relationship between Jitter and Phase Noise 129 137 142 143 145 147 153 157 157 158 161 161 161 ix B Power Spectral Density of the Output C The ISF of an Ideal LC Oscillator D Calculation of the ISF D.1 D.2 Direct Impulse Response Calculation Calculation of the Impulse Response from the Steady-State Solution E Phase Noise and Jitter in Phase-Locked Loops E.1 A Brief Review of PLLs E.1.1 First Order Loop THE DESIGN OF LOW NOISE OSCILLATORS Higher Order Loops Frequency Multiplication E.2 Phase Noise and Jitter in PLLs VCO Noise Other Sources of Noise E.1.2 E.1.3 E.2.1 E.2.2 E.2.3 E.2.4 E.2.5 Phase Noise and Jitter in First Order Loops Jitter and Phase Noise in Higher Order Loops The Effect of the Frequency Divider F Describing Function Analysis of Oscillators Bibliography 163 167 179 187 169 169 170 170 175 177 x