آرایه پردازنده جاسازی شده قابل برنامه ریزی برای برنامه های چند رسانه ای / Customizable embedded processor array for multimedia applications

آرایه پردازنده جاسازی شده قابل برنامه ریزی برای برنامه های چند رسانه ای Customizable embedded processor array for multimedia applications

  • نوع فایل : کتاب
  • زبان : انگلیسی
  • ناشر : Elsevier
  • چاپ و سال / کشور: 2018

توضیحات

رشته های مرتبط فناوری اطلاعات
گرایش های مرتبط سیستمهای چند رسانه ای
مجله یکپارچگی، VLSI
دانشگاه Department of Electronics&Communication Engineering – Istanbul Technical University – Turkey

منتشر شده در نشریه الزویر
کلمات کلیدی آرایه پردازنده قابل برنامه ریزی، دستورالعمل انعطاف پذیر، سخت افزار پردازش تصویر، دامنه محاسبات خاص

Description

1. Introduction Computing hardware design methodology has evolved significantly over the years. As chips get larger and complexity of each design increases, flexibility and quick time to market in the form of reprogrammable/reconfigurable chips and systems increase in importance [1]. Several Multi Processor System on a Chip (MPSoC) and CoarseGrained Reconfigurable Architectures (CGRA) have been proposed in recent years [2–4]. Using CGRAs may be preferred for several reasons such as speed, area, power or IP re-usability [3]. Furthermore, comparing to Field Programmable Gate Arrays (FPGA), CGRAs have a shorter reconfiguration time. CGRAs are suitable for systems that require intensive computations. By adjusting the number and structure of processing elements on a CGRA, we can obtain an architecture that meets the requirements of the computation. Image/video processing is an area where algorithms need intensive computation with high performance. Handling this kind of computation usually requires custom hardware [5]. Considering today’s technology, every portable device tends to have a camera, e.g. glasses, watches, smart phones, etc. Each device has its own configuration and requires mostly different features. Designing dedicated hardware for image processing tasks for every device is time consuming and not economically feasible at all. In most devices, image processing tasks are handled using System-on-Chips (SoC) with DSP or GPU cores. If a designer chooses to use commercial SoCs, he/she has to accept what the chip offers, in terms of speed and power dissipation. Those architectures may include redundant parts that might not be used at all. This redundancy leads to extra chip area usage and power dissipation. On the other hand, implementing an image processing task on a CGRA yields efficient results in terms of area, power dissipation, or speed comparing to commercial SoCs [6]. Time-to-market of an image/ video processing system, which is implemented on customizable cores like CGRAs, is less than that of a custom Application Specific Integrated Circuit (ASIC) [7]. Besides, it is easy to adopt such systems for later alterations. Consequently, we can say that CGRAs are suitable for image/video processing tasks of low power, low cost consumer electronics.
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